Semiconductor memory devices generally consist of an array of memory cells and associated control circuitry. Each memory cell may consist of one or more transistors and the control circuitry may include word line drivers and bit line drivers. The array of memory cells may be arranged in a two-dimensional array such that any particular memory cell is located at the intersection of a particular row-column address. The row-column address may be selected using the corresponding word line driver and bit line driver. Typically, the word line driver is coupled to the gates of each transistor in a specified row and the bit line drivers are coupled to the source/drain of each transistor in a specified column. Accordingly, by applying different combinations of signals to the word line drivers and the bit line drivers, individual memory cells can be selected and controlled.